The phase-locked loop is a versatile semiconductor circuit used to generate an output signal, such as a clock signal, whose phase is related to the phase of an input signal, such as a reference clock. A phase-locked loop typically consists of several blocks including a phase/frequency detector 10, loop filter 20, an oscillator 30, and frequency divider 40.
The frequency of the oscillator is tunable, and typically controlled by an input voltage or current. The most common type of a frequency tunable oscillator used in phase-locked loops is the type whose frequency is controlled by an input voltage, and is referred to as a voltage controlled oscillator.
The phase/frequency detector 10 compares the phase of the reference clock and the local clock, which is typically the output of the frequency divider 40, as indicated in FIG. 1.
Conventionally, the phase/frequency detector 10, charge-pump and loop filter 20 have been primarily implemented with ‘analog’ circuit structures. These phase-locked loops are referred to as ‘analog phase-locked loops’.
Recently, aided by ongoing semiconductor technology and process scaling, an alternate phase-locked loop architecture has emerged that leverages extensive digital signal processing. These ‘digital phase-locked loop’ architectures are functionally equivalent, but have different implementations for some of the sub-blocks.
FIG. 3 shows a basic prior art digital phase-locked loop architecture where the analog phase/frequency detector is replaced with a digital phase/frequency detector 120, and the charge-pump and analog loop filter are replaced with a digital loop filter 130 and a digital-to-analog converter 160.
The digital components are designed to mirror the functions of their analog counterparts, and the phase-locked loop locking dynamics are similar.
In the prior art, the core digital loop filter is implemented with a proportional and integral path that mimics an analog loop filter which can be represented in the Z domain with the following transfer function:
      Y    ⁡          (      z      )        =            [              α        +                  β          ⁢                      1                          1              -                              z                                  -                  1                                                                        ]        ⁢          X      ⁡              (        z        )            where α represents the proportional term, β represents the integral term, X(z) represents the output of the phase/frequency detector and Y(z) represents the output of the loop filter.
Such a digital loop filter can be modeled in discrete time as:y[n]=y[n−1]+αx[n]−αx[n−1]+βx[n]
In prior art, there are separate, non-linear control loops which are used for coarse frequency locking, determining phase-locked loop design parameters, or adjusting the values of α or β in real-time; however, the core loop filter does not include algorithms to non-linearly alter the loop filter output in response to phase/frequency detector transitions.
FIG. 4 shows a prior art digital phase-locked loop architecture with a coarse/fine segmented digital-to-analog converter. A challenge in digital phase-locked loops is achieving the high digital-to-analog converter resolution that is required to achieve very precise frequency steps.
Conventional devices have achieved a high digital-to-analog converter resolution by dividing a high resolution digital-to-analog converter into multiple digital-to-analog converter segments of reduced resolution.
When there are two digital-to-analog converter segments, these digital-to-analog converter segments can be referred to as a coarse digital-to-analog converter 161 (digital-to-analog converter A) and a fine digital-to-analog converter 162 (digital-to-analog converter B).
Conventionally, during normal phase-locked loop operation the coarse digital-to-analog converter first converges and then the fine digital-to-analog converter is updated. This method of operation is referred to as sequential operation within this document.
Once the coarse digital-to-analog converter has converged, it no longer updates unless the fine digital-to-analog converter saturates or nears saturation, at which time the coarse digital-to-analog converter is updated to prevent the fine digital-to-analog converter from saturating. When the coarse digital-to-analog converter is updated, any mismatch between the coarse digital-to-analog converter and the fine digital-to-analog converter can result in a frequency error and degrade phase-locked loop performance.
An additional challenge facing both digital and analog phase-locked loops is a fundamental trade-off between phase-locked loop settling time and loop filter bandwidth.
It is often desirable to have low loop filter bandwidths to reduce phase noise while the phase-locked loop is locked, but this comes at the cost of degraded settling time.
A conventional technique to improve this trade-off is to dynamically vary the loop bandwidth while settling. During coarse frequency lock, conventional digital phase-locked loops use non-linear algorithms to decrease the phase-locked loop settling time compared to a linear algorithm; however, once the coarse sequence of lock is complete, conventional digital phase-locked loops employ linear control loops which can result in degraded settling time, especially at low digital phase/frequency detector resolutions.